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Architecture

The architecture of the 5-stage RISC-V core is detailed in the diagram below. Module and signal names are kept consistent with the SystemVerilog source files for direct cross-referencing.

Architecture diagram

The following sections will cover the implementation details of the various models, assuming a foundational understanding of computer architecture. For a comprehensive introduction to these concepts applied to the RISC-V ISA, the following references are recommended:

  • "Digital Design and Computer Architecture" (RISC-V edition) by S. Harris and D. Harris
  • "Computer Organization and Design" (RISC-V edition) by D. Patterson and J. Hennessy

Register file

ALU

Control unit